A clocked bistable circuit, such as a latch device or flip-flop, may require an indeterminate amount of time to generate a valid output when switching states. When input changes randomly with respect to the clock driving the digital circuit, such as when asynchronous input is received, there is a small probability that the output will exhibit an unpredictable delay. This happens when the input transition not only violates the setup and hold-time specifications, but also occurs within the window of time when the digital circuit accepts the new input. Under these circumstances, the bistable circuit can enter a balanced transitory state, called a metastable state.
A metastable state is not stable, and eventually a small deviation from an equal balance will cause the output to revert to one of the stable states. The time required for the circuit to resolve to a stable state depends on the metastability time-constant, tau (i), and is the dominant factor in determining the mean time between failures (MTBFs).
Tau of a specific circuit depends on several characteristics, such as the parasitic capacitances in the circuit, the gate lengths of the transistors, etc. Tau is generally proportional to the amount of energy expended per unit time while resolving to one of the two stable operating states. This is reflected in a power-supply-related term for tau. Low voltage levels of a device may cause tau recovery time to increase and can be a significant problem for mobile and other battery operated devices.
For example, in a CMOS bistable latch, there is a dependence on MOS transistor thresholds for CMOS circuits of the form:Tau≈Constant/(Vsupply−2*Vth)N where Vsupply is the supply voltage to the latch circuit, Vth is the threshold voltage, and N is an exponential factor between 1 and 2. As Vsupply is reduced toward (2*Vth), tau increases. As process geometries shrink, supply voltages are decreased to increase power efficiency, and as clock speeds are increased, the impact of metastability becomes more significant.
Some methods attempt to compensate for latch metastablity by implementing several latches in series, thereby transferring the decision of one latch to the next. These solutions may simply transfer a potential metastable state from one latch to the next, allowing more time for resolution, but they also insert extra clock delays (latency) in the system which are often undesired.